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15.1. I C Overview .................................................................................................................................... 145
15.2. I C-Bus Example ............................................................................................................................... 145
15.3. I C START and STOP Conditions ......................................................................................................... 146
15.4. I C Bit Transfer on I C-Bus ................................................................................................................. 146
15.5. I C Single Byte Write to Slave ............................................................................................................. 147
15.6. I C Double Byte Read from Slave ......................................................................................................... 147
15.7. I C Single Byte Write, then Repeated Start and Single Byte Read ............................................................... 147
15.8. I C Master Transmitter/Slave Receiver with 10-bit Address ........................................................................ 148
15.9. I C Master Receiver/Slave Transmitter with 10-bit Address ........................................................................ 148
15.10. I C Master State Machine .................................................................................................................. 151
15.11. I C Slave State Machine ................................................................................................................... 158
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List of Figures
3.1. Diagram of EFM32G .............................................................................................................................. 7
3.2. Energy Mode indicator ............................................................................................................................. 7
4.1. Interrupt Operation ................................................................................................................................ 11
5.1. EFM32G Bus System ............................................................................................................................ 14
5.2. System Address Space .......................................................................................................................... 14
5.3. Write operation to Low Energy Peripherals ................................................................................................ 19
5.4. Read operation form Low Energy Peripherals ............................................................................................. 20
6.1. AAP - Authentication Access Port ............................................................................................................ 24
7.1. Revision Number Extraction .................................................................................................................... 30
8.1. DMA Block Diagram .............................................................................................................................. 39
8.2. Polling flowchart .................................................................................................................................... 42
8.3. Ping-pong example ................................................................................................................................ 44
8.4. Memory scatter-gather example ............................................................................................................... 47
8.5. Peripheral scatter-gather example ............................................................................................................ 49
8.6. Memory map for 8 channels, including the alternate data structure ................................................................. 51
8.7. Detailed memory map for the 8 channels, including the alternate data structure ................................................. 52
8.8. channel_cfg bit assignments ................................................................................................................... 53
9.1. RMU Reset Input Sources and Connections. .............................................................................................. 78
9.2. RMU Power-on Reset Operation .............................................................................................................. 79
9.3. RMU Brown-out Detector Operation .......................................................................................................... 79
10.1. EMU Overview .................................................................................................................................... 84
10.2. EMU Energy Mode Transitions .............................................................................................................. 85
11.1. CMU Overview .................................................................................................................................... 94
11.2. CMU Switching from HFRCO to HFXO before HFXO is ready ...................................................................... 97
11.3. CMU Switching from HFRCO to HFXO after HFXO is ready ........................................................................ 98
11.4. HFXO Pin Connection .......................................................................................................................... 98
11.5. LFXO Pin Connection .......................................................................................................................... 99
11.6. HW-support for RC Oscillator Calibration ................................................................................................ 100
13.1. PRS Overview ................................................................................................................................... 127
13.2. TIMER0 overflow starting ADC0 single conversions through PRS channel 5. ................................................. 129
14.1. EBI Overview .................................................................................................................................... 135
14.2. EBI Non-multiplexed 8-bit Data, 8-bit Address Read Operation ................................................................... 135
14.3. EBI Non-multiplexed 8-bit Data, 8-bit Address Write Operation ................................................................... 136
14.4. EBI Address Latch Setup .................................................................................................................... 136
14.5. EBI Multiplexed 16-bit Data, 16-bit Address Read Operation ...................................................................... 136
14.6. EBI Multiplexed 16-bit Data, 16-bit Address Write Operation ...................................................................... 137
14.7. EBI Multiplexed 8-bit Data, 24-bit Address Read Operation ........................................................................ 137
14.8. EBI Multiplexed 8-bit Data, 24-bit Address Write Operation ........................................................................ 137
2
2
2
2 2
2
2
2
2
2
2
2
16.1. USART Overview ............................................................................................................................... 178
16.2. USART Asynchronous Frame Format .................................................................................................... 179
16.3. USART Transmit Buffer Operation ........................................................................................................ 183
16.4. USART Receive Buffer Operation ......................................................................................................... 185
16.5. USART Sampling of Start and Data Bits ................................................................................................ 186
16.6. USART Sampling of Stop Bits when Number of Stop Bits are 1 or More ....................................................... 186
16.7. USART Local Loopback ...................................................................................................................... 187
16.8. USART Half Duplex Communication with External Driver ........................................................................... 188
16.9. USART Transmission of Large Frames .................................................................................................. 189
16.10. USART Transmission of Large Frames, MSBF ...................................................................................... 190
16.11. USART Reception of Large Frames ..................................................................................................... 190
16.12. USART ISO 7816 Data Frame Without Error ......................................................................................... 192
16.13. USART ISO 7816 Data Frame With Error ............................................................................................. 192
16.14. USART SmartCard Stop Bit Sampling .................................................................................................. 193
16.15. USART SPI Timing .......................................................................................................................... 194
16.16. USART Example RZI Signal for a given Asynchronous USART Frame ....................................................... 197
18.1. LEUART Overview ............................................................................................................................. 220
18.2. LEUART Asynchronous Frame Format .................................................................................................. 221
18.3. LEUART Transmitter Overview ............................................................................................................. 223
18.4. LEUART Receiver Overview ................................................................................................................ 225
18.5. LEUART Local Loopback .................................................................................................................... 228
18.6. LEUART Half Duplex Communication with External Driver ......................................................................... 228
2011-04-12 - d0001_Rev1.10
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